The present invention relates to an interleave control power supply device for performing power factor correction (PFC) and a control circuit. Particularly, it relates to a switching power supply device which converts an AC power supply as an input into a DC output with a high power factor by using an interleaved switching control technique.
It is well-known that AC power includes active power, reactive power and apparent power, but active power is the only power which can be converted for AC/DC conversion. Accordingly, more power can be converted into DC as the power factor is larger (close to 100%). It is therefore general that attention is paid to PFC (Power Factor Correction) when an efficient switching power supply device must be designed. In addition, PFC as a harmonic reducing circuit has become important with the advance of restrictions on harmonics in recent years.
There has been heretofore known a PFC boost converter for controlling a stable output voltage while generating an input current proportional to an input voltage by using a boost circuit. As control modes for controlling switching elements in such a PFC boost converter, there are known a (current) discontinuous mode, a (current) continuous mode and a critical mode separated by a current flowing in an inductor.
A critical single mode and a critical interleave mode have been known as the critical mode. Generally, in an interleave control technique, the phase difference between two converter circuits (a master and a slave) must be 180° to suppress ripples of an output voltage and an output current and a peak value of output power. A critical interleave control technique for performing digital controlling has been disclosed in US Patent Application Publication No. 2007/2532323. A critical interleave control technique for performing analog controlling has been disclosed in US Patent Application Publication No. 2007/2532324, JP-A-10-127049 and JP-A-10-146049.
The digital technique disclosed in US Patent Application Publication No. 2007/2532323 is a technique which measures a switching cycle based on a clock cycle to obtain a phase difference of 180°, that is, a half cycle. In order to keep sufficient accuracy, the clock cycle needs to be sufficiently smaller than the switching cycle. In order to achieve this condition, it is necessary to increase the number of digital bits. For this reason, the problem of increase in circuit scales occurs.
The analog technique disclosed in US Patent Application Publication No. 2007/2532324 requires independent switching control circuits for respective phases. This causes a problem that a long delay is required before the phase difference between respective phases reaches a predetermined phase difference. Moreover, a phase difference detecting circuit is so complex that phase control accuracy is lowered. This causes a problem of increase in circuit scale. Specifically, in a circuit shown in FIG. 4 in US Patent Application Publication No. 2007/2532324, a phase difference holding circuit 390 is provided for holding a phase difference of 180° between two converter circuits 392 and 394. There is a problem that a long time is required before the phase difference holding circuit 390 completes the phase difference control.
In the analog technique disclosed in JP-A-10-127049 and JP-A-10-146049, the timing of a slave signal is determined by detecting the timing of crossing of voltages of two capacitors based on a master signal used as a reference in such a manner that one capacitor is charged while the other capacitor is discharged during one cycle of the master signal. This technique however requires a circuit for detecting the timing of crossing of voltages of two capacitors charged and/or discharged. The discharge-side capacitor needs to have a function of performing rapid discharging at the crossing timing. For this reason, there is a problem that a circuit for generating the slave signal becomes complex while phase control accuracy is low.
That is, in order to obtain a phase difference of 180° between the master and the slave as described above, a charging current and a discharging current and capacitance values of two capacitors need be accurately equalized to each other. Particularly as for capacitors, individual variations in capacitors are unavoidable if the two capacitors are made of discrete parts. Moreover, if an offset voltage exists in a comparator for comparing voltages of two capacitors, there is a problem that the offset voltage will directly cause error in phase difference.
With respect to the current, JP-A-10-127049 has still a problem that accuracy cannot be fully warranted because a current in a time constant circuit of CR is used. Incidentally, because a constant current source is used in FIG. 9 in JP-A-10-146049, it is conceived that current accuracy can be warranted.
To overcome the problems in the background art, an object of the invention is to provide an interleave control power supply device having an interleave control circuit of a simple analog interleave control technique that can achieve high phase control accuracy and small circuit scale, and a control circuit and method for the power supply device.
Further objects and advantages of the invention will be apparent from the following description of the invention.